In the manufacture of integrated circuits, copper interconnects are used to couple various circuit devices, such as transistors and capacitors. Copper interconnects are generally formed on a semiconductor substrate using a copper damascene process (e.g., a dual damascene process which is well known in the art). In this process, a trench is etched into a dielectric layer and the trench is filled with a barrier layer, an adhesion layer, and a seed layer. For instance, a physical vapor deposition (PVD) process, such as a sputter process, may be used to deposit a non-conformal tantalum nitride barrier layer and a non-conformal tantalum adhesion layer (i.e., a TaN/Ta stack) into the trench. This may be followed by a PVD sputter process to deposit a non-conformal copper seed layer into the trench. A plating process may then be used to fill the trench with copper metal and a chemical mechanical polishing (CMP) process may be used to remove excess metal and complete formation of the interconnect.
Copper interconnects that are formed by conventional damascene processes tend to suffer from issues such as micro-voids and seams. This is a result of using two separate processes to form the copper interconnect, the first being the PVD seed layer deposition and the second being the plating trench fill deposition. The use of two separate deposition processes creates other issues as well, such as increased throughput time, increased wafer handling, and reduced copper film quality. Accordingly, alternate deposition methods for copper metal into a trench are needed.